The present disclosure relates to solid-state imaging devices, and more particularly to techniques of converting light reception signals obtained by photoelectric conversion to digital signals and outputting the signals outside chips.
In recent years, with a dramatic increase in the pixel number of a solid-state imaging device, high-speed reading of signals from the solid-state imaging device has been increasingly demanded.
In an initial MOS solid-state imaging device, an analog signal obtained in a pixel circuit as a result of photoelectric conversion was read outside from a solid-state imaging device, and the analog signal is converted by an external analog-digital (AD) converter, thereby obtaining a digital signal. With this configuration, however, an improvement in the reading speed is limited due to floating capacitance existing inside the solid-state imaging device.
In order to address the problem, a technique is suggested, which increases the speed of outputting signals by converting analog signals generated in a pixel circuit to digital signals in a solid-state imaging device to reduce influences of floating capacitance, etc. (See, for example, Japanese Patent Publication No. 2005-323331).
FIG. 7 is a schematic block diagram illustrating a configuration of a major portion of the solid-state imaging device shown in Japanese Patent Publication No. 2005-323331. The solid-state imaging device converts a signal voltage from a unit pixel 101 to a digital signal by single-slope AD conversion. Rough operation of the solid-state imaging device will be described below.
The unit pixel 101 in an imager 103 applies a signal voltage obtained by photoelectric conversion to one input terminal of a comparator 105. A reference signal generator 107 generates a ramp signal using, for example, a digital-analog (DA) converter, and applies the signal to the other input terminal of the comparator 105. The voltage of the ramp signal monotonically rises in synchronization with a clock signal CK supplied by a timing controller 109. For example, a counter flip-flop 109, which is indicated by “T-FF” in FIG. 7, starts counting the clock signal CK in synchronization with the start of the rise of the ramp signal voltage. When the level of a signal (i.e., a comparison result signal shown in FIG. 7) indicating that the level of the ramp signal from the comparator 105 coincides with the signal voltage from the unit pixel 101 changes, the counter flip-flop 109 outputs the count value at that time as a digital signal indicating the signal voltage output from the unit pixel 101.